This application claims benefits of priority under 35 USC 119 to Japanese Patent Application No. 2000-087388 filed on Mar. 27, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor device having memory cells including ferroelectric capacitors, and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Recently a ferroelectric memory which consists of series connected memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor in-between said two terminals, hereafter named xe2x80x9cSeries connected TC unit type ferroelectric RAMxe2x80x9d has been introduced by D. Takashima et. al in JSSCC, pp. 787-792, May, 1998. This memory is effective to reduce a total chip size.
FIG. 14 is a circuit diagram showing part of a memory cell area of such a Series connected TC unit type ferroelectric RAM.
This ferroelectric memory has a 2.5-V bit line BL and a 0-V plate line PL. Between the lines BL and PL, a select gate 50 and ferroelectric memory cells 60-1, 60-2, and the like are connected in series. Each of the ferroelectric memory cells, for example, 60-1 has a MOSFET 61-1 and a ferroelectric capacitor 62-1. The MOSFETs 61-1, 61-2, and the like are connected to word lines WL1, WL2, and the like, respectively, and are usually in an ON state to charge the ferroelectric capacitors to 0 V.
To write data into a target memory cell, a select gate 50 corresponding to the target memory cell is turned on, and the MOSFET of the target memory cell is turned off, to charge the ferroelectric capacitor of the target memory cell to 2.5 V.
One of the structural characteristics of the Series connected TC unit type ferroelectric RAM is that source/drain regions on each side of a gate electrode of a memory cell transistor are connected to the upper and lower electrodes of a ferroelectric capacitor, respectively.
FIG. 15 partly shows the structure of the Series connected TC unit type ferroelectric RAM of the prior art. A memory cell transistor (MOSFET) 61 has first and second source/drain regions 103. On the first source/drain region 103, a plug electrode 104 is formed. On the plug electrode 104, a lower electrode 105, a ferroelectric film 106, and an upper electrode 107 form a layered structure serving as a ferroelectric capacitor. The first source/drain region 103 is connected to the lower electrode 105 of the ferroelectric capacitor through the plug electrode 104, and the second source/drain region 103 is connected to the upper electrode 107 of the ferroelectric capacitor through a metal contact 108b, a metal wire 109, and a metal contact 108a. 
The ferroelectric memory of this prior art realizes a series connected structure by opening a contact hole for the contact 108b on each second source/drain region 103.
After opening a contact hole on each upper electrode 107, it is preferable to carry out annealing in an oxidizing atmosphere to cure the ferroelectric film 106 which may have been damaged during the opening of the contact holes. At this time, the annealing may oxidize the source/drain region 103 if the region is exposed at the bottom of a contact hole for the contact 108b. This should be avoided, and therefore, it is difficult to carry out the curative annealing after opening contact holes according to the prior art.
In addition, the contact 108b is close to the lower electrode 105, and when forming fine memory cells, an etching gas used by reactive ion etching (RIE) to open contact holes will damage the lower electrodes 105 of ferroelectric capacitors.
Another problem is the long contacts 108b. Due to the length, each contact 108b tends to be tapered to provide insufficient conductivity.
An object of the present invention is to provide a semiconductor device having ferroelectric memory cells, capable of carrying out recovery annealing even after opening contact holes, to provide proper ferroelectric capacitor characteristics.
Another object of the present invention is to provide a method of manufacturing such a semiconductor device having ferroelectric memory cells.
In order to accomplish the objects, a first aspect of the present invention provides a semiconductor device having ferroelectric memory cells. The semiconductor device includes memory cell transistors formed on a semiconductor substrate. Each of the memory cell transistors includes first and second source/drain regions. On the first source/drain region, a first plug electrode is formed, and on the second source/drain region, a second plug electrode is formed. On the first plug electrode, a first lower electrode, a ferroelectric film, and an upper electrode form a layered structure serving as a ferroelectric capacitor. On the second plug electrode, a second lower electrode is formed from the same layer film that forms the first lower electrode. The upper electrode and the second lower electrode are electrically connected to each other through at least a contact and wiring.
A second aspect of the present invention provides a method of manufacturing the above-mentioned semiconductor device having ferroelectric memory cells. The method forms memory cell transistors on a semiconductor substrate, covers the surface of the semiconductor substrate with a first insulating interlayer, opens contact holes corresponding to source/drain regions of the memory cell transistors through the first insulating interlayer, and fills the contact holes with electrode material to form first and second plug electrodes in contact with the source/drain regions. On the surface of the substrate processed as mentioned above, the method forms a lower electrode layer, a ferroelectric film, and an upper electrode layer in this order, patterns the upper electrode layer to form a pair of upper electrodes for each memory cell, and patterns the ferroelectric film and lower electrode layer to form ferroelectric capacitors each including, on the first plug electrode, a first lower electrode, a ferroelectric film, and a pair of upper electrodes. At this time, second lower electrodes are also formed on the second plug electrodes, respectively. Thereafter, the method forms wiring and contacts to electrically connect each upper electrode to a corresponding one of the second lower electrodes.
To form the wiring and contacts, the method forms a second insulating interlayer on the substrate on which the second lower electrodes have been formed, opens contact holes and/or wiring trenches in the second insulating interlayer, and fills the contact holes and trenches with a conductive film serving as the wiring and contacts.
According to the first and second aspects, the opening of the contact holes and wiring trenches exposes no source/drain regions or plug electrodes, which are composed of oxidizable material in high temperature oxidizing atmosphere. Therefore, without damaging the source/drain regions and plug electrodes, the method can achieve annealing in a high-temperature oxidizing atmosphere to cure the ferroelectric film damaged by the opening of the contact holes and trenches and improve the characteristics of the ferroelectric film.